1. Field
Various features relate to memory devices and, in particular, a memory cell array with reserved sectors for storing configuration information, including failed address information, for the memory cell array.
2. Background
FIG. 1 illustrates a typical cell array for a memory device. In one example, the memory device may be a non-volatile memory device that includes one or more cell arrays. The cell array 102 may comprise a first cell array 101a and/or second cell array 101b that are accessible from a single decoder 103 or separate decoders. The cell array 102 may comprise one or more word lines (WL) 104 and one or more bit lines 105 crossing/intersecting the word lines 104, and electrically rewritable and non-volatile memory cells 107 disposed at the crossings between the word lines 104 and bit lines 105 and capable of storing a plurality of bits (e.g., one bit per bit cell). The decoder 103 may serve to decode an input address and select a corresponding appropriate word line and bit line (e.g., column and row). That is, the selection of a word line and bit line combination permits storage of a bit at a particular address. The cell array 102 may also comprise a redundancy system to “repair” failed word lines by using one or more redundant word lines (RWL) 108 accessed via a word line redundancy module 106. Upon detection of a failed word line 109, the address(es) corresponding to that failed word line 109 are mapped, assigned, and/or redirected to a redundant word line 108. The redundancy system may also include an internal or external fuse block 110 (e.g., one-time programmable or non-volatile storage) that stores failed address information for the cell array 102 and an exclusive (EX) OR module 112. The EXOR module 112 may compare an input address 116 to the failed address(es) in the fuse block 110. Upon the occurrence of a read/write operation to the cell array 102, the input address 116 is provided to the EXOR module 112. If an input address 116 is found in the fuse block 110, then the write/read operation is routed to the redundant word line (RWL) 108 in the cell array 102.
FIG. 2 illustrates that the typical cell array 102 for the memory device may also use fuse blocks 202a, 202b, and 202c for other purposes. For proper memory device operation, certain information is needed, such as a chip identifier, timing trimming, and/or voltage trimming. Such information is often stored in fuse blocks inside and/or outside of the memory device. In addition to failed address information (e.g., tow/column and/or IO repair), additional fuse blocks 202a, 202b, 202c may serve to store: (a) chip identifier (ID) information, (b) timing and/or voltage/current options, and/or (c) other functional options.
The use of internal or external fuse blocks with memory devices has several problems. For instance, internal fuse blocks (e.g., on the same semiconductor die as the cell array) increase the chip size since a fuse block is relatively large. Using external fuse blocks on the same substrate or package) to store failed address information requires a signal bus from the outside fuse block to the cell array.
Consequently, there is a need for an alternative to using fuse blocks with cell arrays in memory devices.